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ICs for TV
AN5367FB
NTSC video, chroma, and deflection signal processing circuit
s Overview
The AN5367FB is an IC to demodulate the NTSC composite signal. It is possible to control the all functions by the I2C bus. The use of flat package allows a space saving in sets design.
14.00.3 12.00.2 36 37 25 24 (1.6)
Unit: mm
s Features
* Luminance signal processing * Incorporating 3.58 MHz trap * Black side gradation control is possible by black expansion circuit * Adopting delay line aperture control * Color signal processing * Incorporating band-pass filter * Incorporating ACC filter * Deflection signal processing * Stable sync. signal generation by the use of double AFC circuit and countdown circuit * Vertical directional screen position is adjustable * Others * Incorporating 3-input composite signal changeover SW * DAC output for adjusting sound volume and screen height
48 13
(1.6)
0.80
0.10.1
0.15 - 0.05
0.35 +0.10 - 0.05
1.950.20
1
12
12.00.2 14.00.3 (1.0)
+0.10
Seating plane
0 to 10 0.50.2
QFP048-P-1212
s Applications
* Color televisions and combined CTV/VCR set
1
AN5367FB
s Block Diagram
Killer filter ABL/ACL Spot killer APC filter OSD-G in OSD-R in OSD-B in
ICs for TV
BL start
BL det.
SC out
36
35
34
33
32
31
30
29
28
27
26
VCCREF VCC1 (9 V) P clamp DAC1 (V height Y in APL det. SCL SDA Killer out Video3 VCC2 (5 V) Video2
37 38 39
25
FSC
C in
24
Limiter R out G out B out YS H out BLK in GND (main) FBP in L det. filter H VCC (6.2 V) H AFC1
Chroma RGB
23 22 21 20
40 41
Video
42 43 44 45 46 47 48 SW
Mute
19 18
I2C Sync.
17 16 15 14 13
10
11 X-ray
DAC2 (sound)
Hold down ref.
GND (Jungle)
Video out
L det. out
Video1
V out
VSYNC in
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Description Video signal input pin 1 Vertical signal clamp pin Video signal output pin DAC output pin 1 Vertical sync. separation input pin Horizontal sync. separation input pin Hold down reference voltage pin Lock detection output pin GND pin (sync. system) Vertical pulse output pin Pin No. 11 12 13 14 15 16 17 18 19 20 Description Hold down input pin Horizontal oscillation pin Horizontal AFC1 filter pin Horizontal stabilized power supply pin (6.2 V) Lock detection filter pin FBP input pin GND pin Blanking pulse input pin Horizontal pulse output pin YS input pin
2
HSYNC in
H OSC
VSYNC
12
1
2
3
4
5
6
7
8
9
ICs for TV
s Pin Descriptions (continued)
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 B output pin G output pin R output pin Output limiter pin Chroma oscillator pin Spot killer pin External B input pin External G input pin External R input pin Chroma APC filter pin Subcarrier output pin Killer filter pin ABL/ACL input pin Black extension start adjusting pin Description Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description
AN5367FB
Black level detection filter pin Chroma signal input pin VCC1 reference voltage pin (9.6 V) Power supply pin (VCC1: 9 V) Capacitor pin for Y clamp DAC output pin 2 Y signal input pin APL detection filter pin SCL pin (for I2C bus) SDA pin (for I2C bus) Killer output pin Video signal input pin 3 Power supply pin (VCC2: 5 V) Video signal input pin 2
s Absolute Maximum Ratings
Parameter Supply voltage VCC Symbol VCC1 (38) VCC3 (47) Supply current ICC I38 I47 I14 I37 Power dissipation *2 Operating ambient temperature Storage temperature
*1 *1
Rating 9.9 5.5 47 31 13 5 775 -20 to +70 -55 to +150
Unit V
mA
PD Topr Tstg
mW C C
Note) *1 : Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2 : The power dissipation shown is the value for Ta = 70C.
s Recommended Operating Range
Parameter Supply voltage Symbol VCC1 VCC2 Supply current I14 I37 Range 8.55 to 9.45 4.75 to 5.25 6.0 to 12 1.0 to 4.5 mA Unit V
3
AN5367FB
s Electrical Characteristics at Ta = 25C
Parameter SW and power supply Circuit current 1 (ICC1) (9 V system) Circuit current 2 (ICC2) (5 V system) 9.6 V reference voltage Operating resistance Zener maximum current SW circuit gain Frequency characteristics Crosstalk Clamp current Total gain Y signal processing Video input pin voltage Y typical output Video voltage gain relative ratio Video voltage gain Video frequency characteristics Picture quality variable range 1 Contrast ratio Brightness variable range V41 EOSTD GY GY fY GS1 GC BR VCC: Typ., input pin voltage measurement Input 2 V[p-p] stair steps As same as the above, G/R, B/R Input 2 V[p-p] stair steps, contrast: typ. Attenuation amount at 6 MHz with f = 1 MHz as reference Input 0.2 V[p-p], sine wave f = 2.5 MHz, sharpness: typ./min. Input 2 V[p-p] stair steps, contrast: max./min. Input: Without input, cut-off: max. , brightness: min. to max. , pedestal level measurement Input: Without input Input 2.0 V[p-p] total white, APL 10% to 90%, DC restoration ratio correction: Off (pin 42: 0 V) VCC: typ. Input signal: Total black, black level detection pin: external RC 9 V, BL start = 20 k 1.1 2.6 -1.0 1.7 -5.0 5.9 6 2.15 1.5 3.2 0 2.1 -2.0 9.0 9 2.40 I38 I47 V37 R37 IVD GSW fSW CT No signal input, I14 = 8 mA, VCC1 = 9 V,VCC2 = 5 V No signal input, I14 = 8 mA, VCC1 = 9 V,VCC2 = 5 V I37 = 2.4 mA I37 = 1.0 mA to 5.0 mA Largest possible sink current f = 1 MHz, 0.7 V[p-p] Attenuation amount at 7 MHz with f = 1 MHz as reference f = 1 MHz, input signal 0.7 V[p-p], sine wave 28 18 9.0 0 5 4.9 -3 -50 6 -19 36 23 9.6 11 5.9 -1.3 10 0 Symbol Conditions Min Typ
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Max
Unit
43 28 10.2 30 6.9 14 +19
mA mA V mA dB dB dB A %
I1 , I46 , Sink current of each input pin, when I48 applying 3 V to pin 1, pin 46 and pin 48 GTOTAL Gain dispersion from each input to output
1.9 3.8 +1.0 2.5 11.4 12 2.80
V V[0-p] dB V[0-p] dB dB dB V
Typical pedestal voltage DC restoration ratio 1
PLSTD TDC1
1.95 94
2.60 100
3.10 106
V %
RGB output BLK level Black level correction amplitude 1
YBLK VBL1
1.0 -100
1.5 0
2.0 +100
V mV
Note) Unless otherwise specified, refer to "* Typical conditions for testing" for the conditions of I2C bus and each pin.
4
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min Typ
AN5367FB
Max
Unit
Y signal processing (continued) Black level correction amplitude 2 Black level correction amplitude 3 VBL2 VBL3 Input signal: Total black, black level detection pin: 3 V, BL start = 20 k Adjust output amplitude to 0.8 V[p-p], black level detection pin: 9 V external RC, BL start = 20 k 0.46 0.10 0.80 0.25 1.14 0.40 V V
Black level correction amplitude 4
VBL4
Adjust output amplitude to 2.0 V[p-p], - 0.1 black level detection pin: 9 V external RC, BL start = 20 k Input 2.0 V[p-p] stair step, B.P.F. SW: On, trap SW: On, measurement of time delay between input and output 330
0
+0.1
V
Y signal delay time
tD1
410
490
ns
Sub-contrast adjustment range 1 Sub-contrast adjustment range 2 Trap attenuation amount Delay line ACL variable range ABL variable range Color signal processing ACC characteristics 1
EOADJ1 Sub-contrast typ. min., input: 2 V[p-p] stair step EOADJ2 Sub-contrast typ. max., input: 2 V[p-p] stair step GTRAP tD ACL ABL f = 3.579545 MHz, trap on/off Difference of amount of delay between B.P.F. on/off Pin 33 7.5 V 2.5 V, stair step 2 V[p-p] Without input, pin 33: 4.5 V 2.5 V, pedestal voltage of RGB output
-40 35 23 90 12 0.4
-30 46 120 20 0.6
-22 55 150 28 0.8
% % dB ns % V
ACC1
Color bar input: 6 dB up, (R-Y) output measurement, burst typical input = 150 mV[p-p] Color bar input: 20 dB down, (R-Y) output measurement, burst typical input = 150 mV[p-p] Level at which demodulation output does not appear when color bar input level is being attenuated. Typical input level: 0 dB Color bar input, color: typ., tint: Center
0.9
1.0
1.1
Times
ACC characteristics 2
ACC2
0.7
0.9
1.1
Times
Color killer tolerance 1
eK1
-53
-43
-34
dB
Color difference output (B-Y) 1 Color difference output (B-Y) 2 Color residue Chroma contrast Free-running frequency APC pull-in range 1 Tint center data
eO1 eO2 eLC CCONT fC0 fAPC TC
1.55 5.2 -300 450 15
2.00 3.7 15 8.2 0 600 1D
2.45 4.5 60 11.2 +300 25
V[0-p] V[0-p] mV dB Hz Hz H
Color bar input, color: max., tint: Center 2.85 Color bar input, color: min. Color bar input, contrast: min. max. For f0 of typical sample, f0 = 3.579545 MHz Color bar: Typical input, B.P.F.: On Rainbow signal, tint data at which B-Y output becomes typical.
Note) Unless otherwise specified, refer to "* Typical conditions for testing" for the conditions of I2C bus and each pin.
5
AN5367FB
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol R/B G/B R G AFSC V31(1) V31(2) ACW KILH KILL KILOP Conditions Tint = min. to max. Rainbow input Rainbow input Reference is B Reference is B fSC component of demodulation output Subcarrier output: Off Subcarrier output: On Output level of fSC Pin 45 voltage measurement, V32 = 5.5 V Pin 45 voltage measurement, V32 = 4 V At VV mode, I45 measurement, V32 = 4 V or 5.5 V V = VR -VG , VG -VB , VB -VR , burst input only, cut off: min. Input: 2.0 V[p-p], total white, contrast: max., cut off: max., bright: max. YS: H, contrast: max., difference from internal pedestal voltage, cut off: min., drive: typ. YS: H, contrast: min., difference from internal pedestal voltage, cut off: min., drive: typ. YS: H, contrast: max., external input clip level difference among R, G and B channel YS: H, contrast: max., input voltage: 0.3 V[p-p], sine wave, 1 MHz Min 30 0.76 0.27 96 225 1.4 5.6 250 4.0 -1 Typ 45 0.96 0.36 104 235 20 1.9 6.1 350 4.6 0.4 0
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Max 1.15 0.45 112 245 50 2.4 6.6 1.0 +1
Unit
Color signal processing (continued) Tint variable range Demodulation output ratio R/B Demodulation output ratio G/B Demodulation angle R Demodulation angle G Demodulation output residual carrier CW output DC level 1 CW output DC level 2 CW Out output level High-level killer output Low-level killer output Killer output open RGB processing RGB output DC difference voltage RGB output limit level External RGB input clip level 1 PL1 VLIM EG1 -300 6.6 2.2 0 6.9 2.6 +300 7.2 3.0 mV V V deg Times Times deg deg mV[p-p] V V
500 mV[p-p] V V A
External RGB input clip level 2
EG2
1.1
1.6
2.1
V
External RGB input clip level difference External RGB gain External RGB frequency characteristics Internal/external pedestal difference voltage YS threshold level Cut-off variable range Drive variable range
EG1
-300
0
+300
mV
GEXT fEXT
1.6
2.3 -1.8
3.0
Times dB
YS: H, contrast: max., input voltage: -4.8 0.3 V[p-p], sine wave, reference: 1 MHz, attenuation amount at 7 MHz Burst input only, YS: high/low Pin 20 voltage at which inside and outside change over Without input, cut off: min. to max. Input: staircase, 2.0 V[p-p], drive: min. to max. 50 1.1 1.2 5
PL2 YS CO DR
250 1.6 1.5 7
600 2.1 1.8 9
mV V V dB
Note) Unless otherwise specified, refer to "* Typical conditions for testing" for the conditions of I2C bus and each pin.
6
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
Parameter Horizontal signal processing Horizontal stabilized power supply voltage Horizontal stabilized power supply maximum current Horizontal stabilized power supply on-state resistance Horizontal output start voltage V14 I14 R14 VFHS Pin voltage, when power supply pin input current I14 = 8 mA Maximum input current for which power supply is stabilized On-state resistance, when input current I14 = 6 mA to 13 mA Horizontal stabilized power supply voltage, when horizontal output pulse becomes 1 V[p-p] or more. Do not apply other power supply voltage. 5.7 13 0 6.1 14 4.5 Symbol Conditions Min Typ
AN5367FB
Max
Unit
6.8 30 5.2
V mA V
Horizontal output pulse duty High-level horizontal output Low-level horizontal output Horizontal output free-running frequency Hor. pull-in range
HO V19H V19L fHO fHP
Horizontal output pulse high level duty 46.9 Horizontal output pulse high level Horizontal output pulse low level 4.0
50.0 4.3 0.2
53.1 4.6 0.5
% V V kHz Hz
Horizontal output frequency, when there 15.45 15.73 16.05 is no horizontal sync. separation input Frequency at which horizontal sync. separation input frequency pulls in. Sync. signal 0.57 V[p-p]. Phase change of horizontal sync. signal and FBP, H-center (0A): 67 60 Phase change of horizontal sync. signal and FBP, H-center (0A): 67 6F Voltage at which X-ray input pin voltage holds down. Hold down pin reference voltage: 6.2 V At horizontal AFC unlocked, RL = 56 k At horizontal AFC locked, RL = 56 k 500 600
Screen position fluctuation 1 Screen position fluctuation 2 Hold Down operation level
HPOS1 HPOS2 VHD
-1.70 -2.12 -2.55 1.97 5.9 2.46 6.2 3.14 6.5
s s V
High-level lock det. output Low-level lock det. output BLK-in input threshold voltage Vertical signal processing Ver. out pulse width High-level ver. out 1 High-level ver. out 2 High-level ver. out 3
LDH LDL
4.5 1.7
2.2
0.7 2.7
V V V
BLKST Pin 18 threshold voltage (BLK is applied to RGB output stage only) VO V10H1 V10H2 V10H3
Pulse width at horizontally/vertically synchronized state Vertical output pulse high level pin 10: open Vertical output pulse high level pin 10: - 0.2 mA Vertical output pulse high level pin 10: - 0.5 mA
610 4.0 3.75 3.3
640 4.3 4.10 3.9
670 4.6 4.60 4.6
s V V V
Note) Unless otherwise specified, refer to "* Typical conditions for testing" for the conditions of I2C bus and each pin.
7
AN5367FB
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min 58 56 Typ
ICs for TV
Max
Unit
Vertical signal processing (continued) Low-level ver. out VOUT free-running frequency Vertical pull-in range VOUT position shift I2 C processing 1.5 I = 3 mA when pull-up resistor is 1.6 k Pin 4 output DC voltage, 0D = 7F Pin 40 output DC voltage, 0C = 7F Pin 4 output DC voltage, 0D = 00 Pin 40 output DC voltage, 0C = 00 8.25 4.5 0.60 0 8.75 5.0 0.90 0.1 3.0 0.4 9.25 5.5 1.20 0.2 V V V V V V V10L fVO fVP VPOS Vertical output pulse low level Ver. out frequency, when there are no hor. and ver. sync. signals input. Sync. input: 2 V[p-p], measurement should be conducted from not pulled in state. V position: min. max. 0 60 31 0.3 62 64 V Hz Hz H
SCL, SDA input threshold voltage VSCL , VSDA Sink capability at ACK High level DAC output 1 High level DAC output 2 Low level DAC output 1 Low level DAC output 2 ACK V4H V40H V4L V40L
Note) Unless otherwise specified, refer to "* Typical conditions for testing" for the conditions of I2C bus and each pin.
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter SW power supply Reference voltage-temperature characteristics SW input dynamic range Input clamp voltage SW output voltage SW output-Y input DC difference voltage SW output-H. Sync. DC difference voltage SW output-V. Sync. DC difference voltage Y signal processing Video maximum output voltage Y signal input dynamic range Picture quality variable range 2
Symbol
Conditions
Min -1.4 6 1.8 2.6 1.0 1.0 1.0
Typ -1.8 2.2 3.0 1.2 1.2 1.2
Max -2.2 2.6 3.4
Unit
V37 /Ta I37 = 2.4 mA, T = -20C to +70C SWD 1 V[p-p] is reference (0 dB), VCC1 = 9 V, VCC2 = 5 V
mV/C dB V V V V V
V1 , V46 , Without input, pin 1, pin 46 and pin 48 V48 voltage V3 Without input, pin 3 voltage V3 -V41 Without input, difference voltage between pin 3 and pin 41 V3 -V6 Without input, difference voltage between pin 3 and pin 6 V3 -V5 Without input, difference voltage between pin 3 and pin 5
EOmax YIN GS2
Brightness: max. Input D range measurement, contrast: typ., sub-contrast: typ. Input: 0.2 V[p-p], sine wave, f = 2.5 MHz, sharpness: max./min.

7.5 4.0 13

V V[p-p] dB
8
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
AN5367FB
Parameter
Symbol
Conditions
Min -300 0.9
Typ 1 53 0 -1.8
Max
Unit
Y signal processing (continued) Contrast fluctuation with picture ASC quality control Brightness relative control sensitivity Black level correction starting point voltage Video signal output supply voltage dependency Output DC voltage ambient temperature dependency Y S/N Service SW operation 1 BR Input: 2.0 V[p-p], stair step, sharpness: max./min. Same as the above G/R, B/R, brightness: min. max. +300 mV[p-p] 1.1 0.25 Times IRE V[p-p]/ V mV/C
VBLSTA BL start external resistor: 20 k EO / VCC Input: 2.0 V[p-p], stair step, output amplitude change of VCC = 5%
EODC / Pedestal level change ratio, when Ta Ta changes from 50C to 75C, contrast: max.,brightness: typ. YS/N Input: 2.0 V[p-p], stair step, noise meter measurement, contrast: max., sharpness: min.
53
55 10
150
dB mV[p-p]
SRSW1 Input: 2.0 V[p-p], stair step, service SW: Measurement of output amplitude, when SW is on. SRSW2 Service SW: On, DC voltage measurement at no-appearance of VOUT . TDC2 f0TRAP TRAP 2.0 V[p-p], stair step, APL det. = 20 k Difference from f = 3.579545 MHz f = 0.5 MHz, comparison of delay amount between trap on/off
Service SW operation 2 DC restoration ratio 2 Trap center frequency Delay amount of trap Temperature characteristics of trap attenuation amount Temperature characteristics of trap frequency ACL start voltage ACL stop voltage ABL start voltage ABL stop voltage Color signal processing Maximum color difference output Free-running frequency supply voltage dependency VCO control sensitivity
3.8 -70 23 -50 -250
4.3 120 40 7.1 2.9 4.0 3.0
4.8 +70 +50 +250
V % kHz ns dB kHz V V V V
GTRAP / f = 3.579545 MHz, -20C to +70C Ta fTRAP / -20C to +70C Ta ACLSTA Pin 33 voltage at which ACL starts to become effective ACLSTO Pin 33 voltage at which ACL stops ABLSTA Pin 33 voltage at which ABL starts to become effective ABLSTO Pin 33 voltage at which ABL stops eOmax fCO / VCC Color bar input, brightness: min., color: max., pedestal to peak voltage VCC = 5% Check change in oscillation frequency, when VAPC = 5.6 V to 5.8 V
4.5 2.8
V[0-p] Hz Hz/mV
9
AN5367FB
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
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Parameter
Symbol
Conditions
Min
Typ -2.9 22.3 1.6 1.1 0 7 4 -12 140 -43 375 40 10 10 5 7.6
Max
Unit
Color signal processing (continued) Free-running frequency ambient fCO /Ta Ambient temperature: -20C to +70C temperature dependency Phase detection sensitivity Phase hold characteristic Demodulation output frequency characteristic Demodulation output supply voltage dependency f-3 {1/ ( x )} x 100 Change amount of tint, when fSC is shifted by 300 Hz Frequency at which color output pin becomes -3 dB Hz/C mV/deg deg/ 100 Hz MHz % % H dB ns dB ns H
eO /VCC Tint: typ., contrast: typ., VCC 5%, color: typ.
Demodulation output ambient eO /Ta Ta = -20C to +70C, +25C is typ. temperature dependency Tint Center shift H.P.F. frequency characteristic H.P.F. group delay amount Color killer tolerance 2 Chroma delay amount C-Y/Y ratio RGB processing Y output amplitude fluctuation EOTRAP 2 V[p-p] staircase input, amplitude (trap on/off) fluctuation at trap on/off Y output amplitude fluctuation (B.P.F. on/off) EOBPF 2 V[p-p] staircase input, amplitude fluctuation at B.P.F. on/off TC fHPF HPF eK2 CHO Change amount of tint center, when B.P.F. is used and not. Gain at f = fSC Group delay amount at f = fSC B.P.F. on state Delay from pin 36 input to pin 21 output
C-Y/Y Color data, when C-Y/Y ratio becomes 1.0
% % % V
Y output amplitude fluctuation EOSHARP 2 V[p-p] staircase input, sharpness: (sharpness) min. max. Spot killer operation Horizontal signal processing Sync. separation clamp voltage Black out operation level V5 , V6 Clamp voltage of sync. separation input pin (pin 5 and pin 6) VBLOUT Voltage at which Y output blacks out when X-ray input pin voltage is raised from 0 V fHD Frequency of HOUT at the time of hold down when X-ray input pin voltage is raised from 0 V VSPK VCC1 voltage at which RBRGB output becomes high, when pin 26 voltage = 8.25 V

1.4 6.3

V V
Operating frequency at hold down BGP start position
16.3
16.4
16.8
kHz
BGPSTA Phase difference from rear edge of hor. sync. to BPG at horizontal AFC loop on
0.3
0.5
0.7
s
10
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
AN5367FB
Parameter
Symbol
Conditions
Min
Typ
Max
Unit s V V s
Horizontal signal processing (continued) BGP pulse width FBP level 1 FBP level 2 FBP delay operating range BGPW VFBP1 VFBP2 FBP BGP width at horizontal AFC loop on AFC operation DC level at FBP input pin HBLK operation DC level at FBP input pin Range of normal operation, when delay amounts are being changed from raise of HOUT to FBP center. 2.5 1.4 0.3 10.0 3.0 2.0 0.7 to 3.5 2.2 1.1 22.0
Horizontal oscillation frequency fHO/Ta Change in ambient temperature from temperature characteristics -20C to +70C Vertical signal processing V. BLK pulse width I2C processing Each DAC precision for 4-bit, 5-bit, 6-bit Each DAC precision for 7-bit, 7+1-bit, (40) excluded Each DAC precision for 7-bit, 7+1-bit, (40) only Each DAC precision for 7+1-bit (7F 80) DAC1 DAC2 DAC3 DAC4 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) VBLKW VBLK width at R,G,B out in horizontall/verticall synchronization
100
Hz
17.0
H
0.1 0.1 -1
1 1 1
1.9 1.9 2 0
LSB/ step LSB/ step LSB/ step %
1LSB = {data (max.) - data (min.)}/ -9.25 -6.25 (2N-1), sub address; 06, 07 (Change amount/total change amount) x 100
* Typical conditions for testing 1. Input signal 1) Video: 10-step staircase, 2.0 V[p-p] 2) Chroma: Color bar signal: Burst level 150 mV[p-p] Rainbow signal: Burst level 150 mV[p-p] 3) Sync. signal: Video signal 1.5 V[p-p] to 2.5 V[p-p] for both horizontal and vertical sync. signal input 2. I2C bus conditions Sub address 00 01 02 03 04 05 06 07 Color Tint Brightness Contrast Sharpness Cut off R Cut off G Cut off B Control Data (H) Sub address 40 20 40 3F 00 00 00 00 11 08 09 0A 0B 0C 0D 0E Control Drive G Drive B Y-adjust, H-center Test, V-position DAC1 DAC2 SW Data (H) 40 40 67 00 40 40 50
AN5367FB
s Electrical Characteristics at Ta = 25C (continued)
* Typical conditions for testing (continued) 3. State of each pin Pin No. 18 20 24 33 34 35 38 42 47 YS Limiter ABL/ACL BL start BL det. VCC1 APL det. VCC2 Symbol BLK in 0V 1.1 V VCC1 7.5 V 20 k VCC1 Applied from outside (9 V) 0V 5V State
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* Functions of SW controlled by I2C bus Data-bit 0E-D0 0E-D1 Functions of SW AV SW changeover D1 D0 Output 0 0 Video1 0 1 Video2 1 0 Video3 1 1 Mute Chroma trap SW (0 without trap) (1 with trap) 0E-D3 Chroma B.P.F. SW (0 without B.P.F.) (1 with B.P.F.) 0E-D4 0E-D7 EE/VV SW D7 D4 0 0 0 1 1 0 1 1 Killer out fSC out Killer result Yes Open No Killer result Yes Open Yes Contents 1. Composite signal changeover Input Video1: Pin 1 Video2: Pin 48 Video3: Pin 46 Output : Pin 3 2. No output at mute 1. Video circuit chroma trap changeover (Y signal phase leads by about 40 ns at trap off (through)) 1. Chroma circuit band-pass filter changeover (Video signal delay amount varies according to B.P.F. on/off) 1. Tuner (EE) and VTR (VV) changeover In principle change over by D4 Tuner (EE): Killer result is output fSC is output VTR (VV): Killer result is not output fSC is not output However, fSC is output if D7 = 1 even at VV. Killer out: Pin 45, fSC out: Pin 31 0E-D5 SSW (service SW) (0 normal) (1 service mode) 1. At service mode (no vertical scanning, white balance adjustment) Vertical output pulse stops (DC about 4.3 V) Y output off, chroma output small 0E-D6 BLK off SW (0 normal) (1 output without BLK) 1. RGB output blanking (BLK) off changeover To be used when RGB output signal without BLK is required.
0E-D2
12
ICs for TV
s Terminal Equivalent Circuits
Pin No. 1
200 200
AN5367FB
Equivalent circuit
38 VCC1 9V 25 A
Description Video signal input pin 1: * Video signal input pin * Typical input 1.0 V[p-p] * Input through capacitor, and sync. top is clamped at 2.2 V * Input video signal with low impedance Vertical signal clamp pin: * Peak clamp pin for separating vertical sync. signal
Voltage AC 1.0 V[p-p]
10 F 1
1.25 k
2.2 V
10 A 2.75 V
2
10 k 10 k 200 2 211 220 2.2 A 30 k 3 k
47 VCC2 5V
AC f = fV
To ver. count down 50 k
3
200
38 100 A
3 400
50 200 100 A
Video signal output pin: * Outputs signals inputted from pin 1, pin 46 and pin 48 * Control of output signal is carried out by I2C bus * Recommended range of use is from -2 mA to +2 mA DAC output pin 1: * Output voltage is adjustable in 128 stages (7-bit organization) by subaddress of I2C bus (0D). * Recommended range of use is from -70 A to +70 A
AC 2.0 V[p-p]
3.0 V
4
12 V 100 A 4 4 k 200 1 k 1 k
38
DC 0.95 V to 8.75 V
40 k
0 A to 200 A
5 6
16 k 400 RV 560 1 F 5 680 pF CV RH 0.1 F 270 6 1200 pF CH
16 k
400
1.75 k 20 A
1.75 k 20 A
Pin 5: Vertical sync. separation input pin: Pin 6: Horizontal sync. separation input pin: 16 k * RV >RH so that slice level is made To H sync. sep. deep for vertical sync. and shallow for To V sync. sep. horizontal sync. * Cutoff frequency determined by RH 1.3 V and CH shall be about 500 kHz. * R large, slice level becomes deeper. (Weak in sync. compression) * R small, slice level is shallow. (Weak in fluctuation such as V sag)
47
AC
2 V[p-p]
13
AN5367FB
s Terminal Equivalent Circuits (continued)
Pin No. 7
760 6.2 V 100 7 1 k 11 10 F 100 A 25 A 1 k 65 k 10 k 50 A 12 V 38 50 A
ICs for TV
Equivalent circuit
Description Hold down reference voltage pin: * Operates hold down by comparing voltage inputted to pin 11 V7 >V11: Normal operation V7 Voltage DC 6.2 V
8
47 5 k 1.2 k 8
5V 56 k
60 k
Lock detection output pin: DC * Pin which outputs whether vertical 0.7 V or less sync. signal of input and HOUT are at lock, synchronizing. 4.5 V or more * Recommended range of use is from at unlock 0 mA to 0.2 mA GND pin: * Sync. system GND AC 4.3 V 0V
9 10
200
47 50 k 20 k 10 43 k 1.8 V 0V
Vertical pulse output pin: * Negative polarity, pulse width 10H * Recommended range of use is from - 0.7 mA to 0 mA
11
760
12 V 38 50 A 6.2 V 100 7 1 k 11 10 F 100 A 25 A 1 k 65 k 10 k 50 A
Hold down reference voltage pin: * Voltage in proportion to a hightension of CRT is applied.
DC
12
270 100 A 435 300 12 CSB 503F38 220 pF (N750) 10 k 10 k 200 A 270
Horizontal oscillation pin: * Oscillates at 32fH 503 kHz by means of ceramic oscillator element * Makes horizontal and vertical pulse by internal countdown circuit of IC.
(503
AC f = 32fH approx. kHz)
14
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 13 Equivalent circuit
14 4.3 V
AN5367FB
Description Horizontal AFC1 filter pin: * Charges and discharges the capacitor connected to pin 13 after comparing the phase of horizontal sync. signal and pulse inside IC. * R1, R2, C1 and C2 are lag-lead filter for AFC1.
Voltage DC typ. 4.3 V
R1 27 k 200 200 Duty 50% 1.5 V 13 Hor. sync. 1 000 A C2 10 F R2 2.2 k C1 0.018 F 2.2 k
27 k
4.4 2.2 k k
4.4 k
fH
Hor. OSC 200 A
Horizontal curve V13
14
12 V 760 14 0.01 F 47 F 6.1 V
Horizontal stabilized power supply pin: * Stabilized power supply for horizontal circuit. A constant voltage circuit is inside. * Recommended range of use is from 6 mA to 12 mA
47
DC 6.1 V
15
200 200 10 k 3.7 V 200 1.5 V 800 A 200 15 0.022 F 10 A 12 k
800 A
Lock detection pin: DC In synchronization * Detects phase of horizontal sync. signal and horizontal output pulse, approx. 4.5 V and outputs the results. In asynchronization * Color control becomes minimum and approx. 0.7 V chroma output becomes zero in asynchronous. * Pin 15 becomes low in out of sync.
16
12 k 100 A 50 A 100 A
39 k 1.95 V 24 k 0.75 V 60 500 k To AFC 40 k
To HBLK
FBP input pin: * FBP input pin for horizontal blanking 50 100 and AFC circuit. A A * Threshold level HBLK: 0.75 V 16 2.7 k AFC: 1.9 V * Burst gate pulse monitor pin 2.7 k Current is flowing out at BGP timing 500 100 k * Voltage input of 0 V or less is inhibited * Recommended range of use is from 0 V to 5 V
47
AC FBP 5V 0V
17
GND pin: * Main GND
15
AN5367FB
s Terminal Equivalent Circuits (continued)
Pin No. 18
5 k 50 A
ICs for TV
Equivalent circuit
38
Description Blanking pulse input pin: * Input threshold voltage: 2.1 V * Operation V18 <1.6 V: Normal operation V18 >2.6 V: RGB outputs are blanked * Recommended range of use is from 0 V to 5 V
Voltage AC 5V 0V
117.5 k 27.5 k
2.7 k 18
100 k 40 k 200
19
300 A
14 200
Horizontal pulse output pin: * Output pulse duty is 50% * Recommended range of use is from -7 mA to 0 mA
AC Pulse 4.3 V 0.2 V
19 40 k
20
1.3 k 50 A 8 k 8 k
38
2.25 V 1.2 k 2.7 k 20 30 k 500 50 A
YS input pin: * Fast blanking input pulse input pin for OSD * Input threshold voltage 1.6 V Low: Normal output High: OSD output * Recommended range of use is from 0 V to 5 V
AC Pulse
21 22 23
100 A
200
38 VCC1 9V
50 R, G, B signal 100 A 200
Pin 21 22 23
Pin 21: B output pin: Pin 22: G output pin: Pin 23: R output pin: * Those are R,G,B output pin * Recommended range of use is from -2 mA to +2mA
AC
1.5 V
24
38 57 k 69 k 24 123 k
Output limiter pin: * This pin determines the voltage to clip high side of R,G,B output. * R,G,B output is clipped at 6.8 V at open. * Recommended range of use is from 0 V to VCC1
DC
16
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 25 Equivalent circuit
38
AN5367FB
Description Chroma oscillation pin: * Pattern of pin and oscillator element should be as short as possible. f = 3.58 MHz
Voltage AC f = fC0 approx. 0.3 V[p-p]
600
600 100 1.5 k 15 pF 25
50 A
500 A 200 A
200 A
26
47.25 k 10 k
38 VCC1
9V 1.75 k 26 1 F 100 k
Spot killer pin: * This is used for quick discharging CRT electric charge, when set power is turned off. * Operating speed varies by changing external capacitance * Recommended range of use is from 0 V to 9 V Pin 27: External B input pin: Pin 28: External G input pin: Pin 29: External R input pin: * External input pin for OSD * Input limit voltage varies according to contrast control level * Recommended range of use is from 0 V to 5.5 V Chroma APC filter pin: * Filter pin for APC detection circuit (operates for BGP period). * External R2 larger, detection sensitivity becomes larger. (It is tends to be pulled in easily but tends to be affected by noise) * Lag-lead filter is organized by R1, R2, C1 and C2
DC
27 28 29
Pin 27, 28, 29 2.7 k 100 200
38 VCC1 25 A To RGB output circuit
AC
0V
VREF
30
38 25 A 200 84 k R1 6.3 V 50 A
DC 5.5 V
30 C1 1 F 3.6 k R2
230
C2 0.027 F
17
AN5367FB
s Terminal Equivalent Circuits (continued)
Pin No. 31
38 25 A 500
ICs for TV
Equivalent circuit
Description
Voltage
200 25 A
31
500
Subcarrier output pin: fSC * Controls output by 0E-D4, D7 of 300 mV[p-p] I2C bus. * There is fSC output. DC: 6.1 V, AC: 350 mV[p-p] DC * There is no fSC output. DC: 1.9 V, AC: 0 mV[p-p] * Recommended range of use is from - 0.4 mA to +0.4 mA
38 500
32
2.7 V 3 k 7.3 k
5.0 V 50 A
Killer filter pin: * Filter pin for killer detection circuit (operates for BGP period) High: Killer on (B&W) Low: Killer on (color)
DC
32 1.25 k 10 k 0.1 F 1.25 k
33
25 A 7V 40 k 4.75 V 25 A 5 k 100 A 40 k 5 k 33
38
ABL/ACL pin: * Apply voltage inversely proportional to brightness of CRT screen. * Operating range is 7 V to 2 V * Controls contrast and brightness in inverse proportion to applied voltage * Recommended range of use is from 0 V to VCC1 Black extension start adjusting pin: * When current flowing out of this pin becomes larger, black extension start point comes closer to white side. * Recommended range of use is from - 0.4 mA to +0.1 mA Black level detection filter pin: * Adjusts black level detection area * Recommended range of use is from 0 V to 8 V
DC
34
20 k 8 k
38
DC
1.2 k
34 20 k
35
5 k 2 k
38
DC
5.18 k 10 k 10 k 6.5 V 35 2.5 k 4.7 F 220 k
18
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 36 Equivalent circuit
38 VCC1 200 5.25 V 20 k 36
AN5367FB
Description Chroma signal input pin: * 2 V[p-p] composite signal in using H.P.F. of IC inside. * Chroma signal of burst = 150 mV[p-p] at externally separating Y/C.
Voltage AC
2 V[p-p] 0.01 F
150 mV[p-p]
200 A 17 A 300 A
37
12 V 1 k 37 0.01 F 100 F 0.01 F 38 VCC1 9.6 V Zener
VCC1 reference voltage pin: * Reference voltage circuit for generating 9 V power supply. * Recommended range of use is from 1.5 mA to 4.5 mA
DC 9.6 V
38
Power supply pin VCC1: * Power supply for chroma, video, RGB and AVSW. * Recommended range of use (typ.: 9 V)
38 1 k
DC
39
5 k 5 k
Capacitor pin for Y clamp: * Clamps the pedestal level of Y signal. * Place clamp capacitor close to pin.
DC
10 A
39 0.01 F
40
2.5 k 2.5 k
38
0 F to 100 F 40 25 k 0.01 F 5 k 10 k
DAC output pin 2: * Output voltage is adjustable in 128 stages (7-bit organization) by I2C subaddress (0C). * External circuit should be high impedance
DC 0 V to 5 V
19
AN5367FB
s Terminal Equivalent Circuits (continued)
Pin No. 41
50 A 200 200
ICs for TV
Equivalent circuit
38
Description Y signal input pin: * Video signal input pin. * Input 2 V[p-p] signal.
Voltage AC
2 V[p-p]
2.75 V 10 F 41 10 A 500
50 A
42
61.2 k 2 k 4 k
38
Y signal APL detection filter pin: * Current flows out according to APL and is smoothed by external CR to generate DC voltage.
DC
42 20 k 4.7 F
43
5V 4.7 k 1 k 43 Clock 30 k 20 A 50 A 3.25 V
47 10 k 51 k 2 k 30 k
SCL pin (for I2C bus): * Low-level input: 1.5 V or less * High-level input: 3.0 V or more * Recommended range of use is from 0 V to VCC2
AC (Pulse)
5V
0V
To logic circuit
44
5V 4.7 k 1 k 44 Data 30 k ACK 2 k 30 k 20 A 50 A 3.25 V
47 10 k 51 k
SDA pin (for I2C bus): * Low-level input: 1.5 V or less * High-level input: 3.5 V or more * ACK sink capability: 3 mA * Recommended range of use is from 0 V to VCC
AC (Pulse)
5V
0V
To logic circuit
47
45
5 k
1 k 45
40 k
Killer output pin: * Output pin of killer detection circuit * Output logic At color: Low At B&W: High However, if 0E-D4 is set at "1" by I2C bus, output becomes open. * Recommended range of use is from -300 A to +300 A
DC
20
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 46
200 200
AN5367FB
Equivalent circuit
38 VCC1 9V 25 A
Description Video signal input pin 3: * Video signal input pin * Typical input 1.0 V[p-p] * Input should be done through capacitor, and sync. top is clamped at 2.0 V. * Video signal should be inputted in low impedance Power supply pin (VCC2: 5 V): * I2 C * To be used for sync. block * Using range from 4.75 V to 5.25 V (typ.: 5 V)
38 VCC1 9V 25 A
Voltage AC
1.0 V[p-p]
10 F 46
1.25 k
2.75 V
10 A
2V
47
DC
48
200 200
10 F 48
1.25 k
2.75 V
10 A
Video signal input pin 2: * Video signal input pin * Typical input 1.0 V[p-p] * Input should be done through capacitor, and sync. top is clamped at 2.0 V. * Video signal should be inputted in low impedance
AC
1.0 V[p-p]
2V
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned. For circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC. 2. The following pins are not resistant to surge so that the precautions should be observed when using this IC. The + side surge withstanding voltage for pin 15, pin 16 and pin 18 is approximately 200 V when a surge source capacitance is 200 pF. Do not apply a surge voltage higher than that.
21
AN5367FB
s Application Circuit Example
ICs for TV
APC filter
ABL/ACL
Killer filter
OSD-R in
BL start
BL det.
OSD-G in
OSD-B in
220 k
C in
SC out
9V
0.027 F
Spot killer
1 F
1 F 3.6 k
FSC
(N750) 15 pF VSXSO190
0.1 F
4.7 F
56 k
0.1 F
100
100
100
9 V Normally open,
36
35
34
33
32
31
30
29
28
27
26
VCCREF
2SD1991A
37
100 F
25
12 V
1 k
0.01 F
requires when adjusting
24
Limiter
100 100 100
VCC1 (9 V) P clamp DAC1 (V height Y in APL det. SCL SDA Killer out
38
0.01 F 0.33 F
Chroma RGB
23 22 21 20
R out G out B out YS H out BLK in GND (main) FBP in
39 40 41
0.01 F 20 k 10 F
Video
42 43 19 18
4.7 F 5V 5V 4.7 k 4.7 k 10 F
44 45 46 47 48
I2C Sync. SW
Mute
17 16 15 14 13
0.022 F 47 F
Video3
100 F
L det. filter
0.01 F 12 V
VCC2 (5 V) Video2
0.01 F 10 F
0.018 F
H VCC (6.2 V) H AFC1
10 F 2.2 k
760
10
11
1 F 5
0.01 F
10 F
0.1 F
220
12
10 F
1
2
3
4
6
7
8
9
680 pF 1 200 pF
2.2 F
12 V
270
L det. out
GND (jungle)
560
560 6V
X-ray
100
CSB503F38 220 pF (N750)
12 V
22
DAC2 (sound)
Hold down ref.
VSYNC
VSYNC in
Video out
HSYNC in
Video1
H OSC
V out

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